In modern integrated circuit (IC) fabrication, layers of material are applied to embedded structures previously formed on semiconductor wafers. Chemical mechanical planarization (CMP) is an abrasive process used to remove these layers and polish the surface of a wafer flat to achieve the desired structure. CMP may be performed on both oxides and metals and generally involves the use of chemical slurries applied via a polishing pad that is moved relative to the wafer (e.g., the pad may rotate circularly relative to the wafer). The resulting smooth, flat surface is necessary to maintain the photolithographic depth of focus for subsequent steps and to ensure that the metal interconnects are not deformed over contour steps. Damascene processing requires CMP to remove metals, such as tungsten or copper, from the top surface of a dielectric to define interconnect structures.
The planarization/polishing performance of a pad/slurry combination is impacted by, among other things, the mechanical properties and slurry distribution ability of the polishing pad and the chemical properties and distribution of the slurry. Often a polishing pad may be porous and/or include grooves to distribute slurry. However, this reduces the overall strength of the polishing pad, making it more flexible and thus reducing its planarization characteristic. Typically, hard (i.e., stiff) pads provide good planarization, but are associated with poor with-in wafer non-uniformity (WIWNU) film removal. Soft (i.e., flexible) pads, on the other hand, provide polishing with good WIWNU, but poor planarization. In conventional CMP systems, therefore, harder pads are often placed on top of softer pads to improve WIWNU. Nevertheless, this approach tends to degrade planarization performance when compared to use of a hard pad alone.
FIG. 1A illustrates “dishing” as a result of applying a flexible polishing pad to wafer 100. The flexible polishing pad provides for a smooth surface but creates dishing 106 by over polishing softer elements, such as copper layer 104, on the surface of substrate 102. The consequence of dishing is an undesirable loss of metal thickness, leading to poor device performance.
Dishing can be reduced or eliminated through the use of a stiffer polishing pad, which can provide greater planarization. Pads may be made stiffer by reducing the number of pores and/or grooves in the pad, however, this can lead to different consequences, for example poor slurry distribution. The net effect may be to increase the number of surface defects 108 on the substrate 102 and/or copper layer 104 (e.g., by scratching and/or pitting the surface/layer), as shown for example in FIG. 1B which illustrates surface defects 108 that may result from application of a relatively stiff polishing pad to wafer 100.
Variations in the above-effects may also be present at different points across a wafer. FIG. 1C shows a cross-section of a wafer 100′ having multiple dies thereon. Assume that a copper layer is present on the top surface of wafer 100′ and that FIG. 1C illustrates the wafer after CMP polishing with a hard pad has occurred. As can be seen, for those dies closer to the center of wafer, the effects of dishing 110, 114 and erosion 112, 116 are less severe than for dies near the edge of the wafer. This is due to the fact that the hard pad must compensate for WIWNU by over-polishing the dies that clear first (i.e., those near the edge of the wafer 100′).
FIG. 1D illustrates the surface of a post-CMP wafer 100″ after polishing with a stacked pad (i.e., one in which a hard pad is placed over a softer pad). In this instance the dishing and erosion of the features at center and edge of the wafer (110″, 112″ and 114″, 116″, respectively) is more severe than occurs near the center of the wafer 100′ illustrated in FIG. 1C, but less so than occurs near the edge thereof. This is due to the fact that while the softer under-pad degrades planarization, polishing is more uniform, leading to more consistent overall performance across the entire surface of the wafer.
It is therefore the case that designing CMP polishing pads requires a trade-off between WIWNU and planarization characteristics of the pads. This trade-off has led to the development of polishing pads acceptable for processing dielectric layers (such as silicon dioxide) and metals such as tungsten (which is used for via interconnects in subtractive processing schemes). In copper processing, however, WIWNU directly impacts over-polishing (i.e., the time between complete removal of copper on any one area versus complete removal from across an entire wafer surface) and, hence, metal loss and, similarly, planarization as expressed by metal loss. This leads to variability in the metal remaining in the interconnect structures and impacts performance of the integrated circuit. It is therefore necessary that both planarity and WIWNU characteristics of a pad be optimized for best copper process performance.
Complicating the optimization process is the ever more prevalent use of low-K materials in modern integrated circuits. Such materials are mechanically fragile and, therefore, require that CMP processes use low down force (i.e., low compressive forces when the wafer is held against the pad during polishing operations). Typical down force pressures used in copper CMP are in the range of 3-5 psi, which is acceptable for processing copper—silicon dioxide interconnects and may be extendable to copper—carbon-doped silicon dioxide interconnects. Moreover, it is known that relatively high CMP down force improves WIWNU (by improving the contact between wafer and the pad). However, for semiconductor process technologies beyond 65 nm nodes (which envision the use of porous, low-K dielectric materials that are mechanically fragile and would be easily damaged by current CMP processes), the use of high down force is not a viable option. Indeed, high local stresses brought about by high down force can result in cracking of the low-K materials or even delamination of the low-K films from the wafer surface. At the same time, using low down force pressure during CMP (to achieve lower stresses) will lead to higher WIWNU, requiring longer polish times and resulting in higher metal losses. The trade-off balance discussed above must therefore take into account the presence of these low-K materials in modern semiconductor devices, and much industry attention is presently being focused on processing techniques that reduce the overall stress on the wafer surface during CMP.
Conventional polishing pads are typically made of urethanes, either in cast form and filled with micro-porous elements or from non-woven felt coated with polyurethanes. During polishing, the pad surface undergoes deformation due to polishing forces. The pad surface therefore has to be “regenerated” through a conditioning process. The conditioning process involves pressing a fine, diamond covered disc against the pad surface while the pad is rotated much like during the polishing processes. The diamonds of the conditioning disc cut through and remove the top layer of the polishing pad, thereby exposing a fresh polishing pad surface underneath.
These concepts are illustrated graphically in FIGS. 2A-2C. In particular, FIG. 2A illustrates a side cutaway view of a new polishing pad 200. Polishing pad 200 contains microelements 204 and grooves 206, much like those found in commercially available polishing pads such as the IC1000 of Rhom & Haas, Inc. FIG. 2B shows the surface 202 of polishing pad 200 after polishing. The top surface of the pad shows degradation 208, especially around the microelements 204 where the edges are degraded due to plastic or viscous flow of the bulk urethane material. FIG. 2C shows the surface 202 of the polishing pad after a conditioning process has been completed. Note the depth of grooves 206 is lower than was the case for the new pad illustrated in FIG. 2A due to material removal during conditioning.
Over multiple cycles of polishing and conditioning, it is usually the case that the overall thickness of a pad wears up to a point such that the pad needs to be replaced. It is evident to those practicing in the art that pad wear rates differ from pad to pad and may also differ from one batch of pads to another batch. Currently no quantitative method exists to determine pad wear, hence end of pad life. Instead, the end of pad life is typically based on visual inspection of the pad surface to check for remaining groove depth. In the case of an un-grooved pad, end of pad life decisions are typically based on the number of wafers polished or the time elapsed since the pad was first put in service. Because such metrics are not particularly accurate it is desirable that a consistent, quantitative means to determine “end of pad life” be implemented. That is, a method based on finite wear of the pad surface would be useful in establishing a consistent basis for pad changes.